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  1. u乐国际娱乐官网 >  解决方案 >  [原创] Intel Cyclone 10 GX FPGA系列开发方案

[原创] Intel Cyclone 10 GX FPGA系列开发方案

关键词:FPGA DSP 工业机器人 可编逻辑控制器(PLC) 时间:2018-01-29 11:18:46       作者:Intel       来源:u乐国际娱乐官网

Intel公司的Cyclone 10 GX FPGA系列是采用高性能20nm技术的低成本器件,具有12.5Gbps芯片-芯片收发器I/O,支持6.6Gbps 底板,高性能1866Mbps外接存储器接口,以及1.434 Gbps LVDS I/O,IEEE 754兼容硬件浮点数字信号处理(DSP)区块,主要用在机器视频,智能视觉相机,工业机器人,工业可编逻辑控制器和Pro-AV系统.本文介绍了Cyclone 10 GX FPGA系列主要优势和特性,器件概述图,收发器架构图以及Intel® Cyclone® 10 GX FPGA开发板主要特性,框图和电路图.

Intel Cyclone 10 GX devices are offered in extended and industrial grades. Extended devices are offered in –E5 (fastest) and –E6 speed grades. Industrial grade devices are offered in the –I5 and –I6 speed grades.

Intel® Cyclone® 10 GX FPGAs are the first low-cost devices built on a high-performance 20 nm process, offering a performance advantage for cost-sensitive applications. The Intel Cyclone 10 GX FPGA features includes:

12.5 Gbps chip-to-chip transceiver I/O support and 6.6 Gbps backplane support 
High-performance 1,866 Mbps external memory interface 
1.434 Gbps LVDS I/Os 
IEEE 754-compliant hard floating-point digital signal processing (DSP) blocks

Cyclone 10 GX FPGA系列主要优势:


Cyclone 10 GX FPGA系列主要特性:



Cyclone 10 GX FPGA系列应用:

Intel Cyclone 10 GX FPGAs are ideal for a broad array of applications requiring increasing levels of core and I/O performance as the need for scalable processing and acceleration increases system requirements.
Machine vision
Smart vision cameras
Industrial robotics
Industrial programmable logic controllers
Pro-AV systems

图1.Cyclone 10 GX FPGA系列概述

图2.Cyclone 10 GX FPGA系列收发器架构图

Intel® Cyclone® 10 GX FPGA开发板

The Intel® Cyclone® 10 GX FPGA Development Kit is a complete design environment that includes both hardware and software you need to develop and evaluate the performance and features of the Intel Cyclone 10 GX FPGA device.

Intel® Cyclone® 10 GX FPGA开发板包括:

This development kit includes a Intel Cyclone 10 GX FPGA device along with the
following components.
Intel Cyclone 10 GX FPGA
• Intel Cyclone 10 GX FPGA device in F780 BGA package
• 780 pin, 29 mm x 29 mm BGA package
• 220K Logic Elements (LEs)
• 12 transceivers capable of 12.5 Gbps data rates
• 284 GPIOs with 118 pairs of LVDS
FPGA Configuration
• Active Serial (ASx4) mode configuration with EPCQ-L
• Fast Passive Parallel (FPP) mode configuration mode by Intel MAX® 10 PFL
• Configuration via PCIe* (CvP) x4 Gen2
Clock Sources
• 50 MHz oscillator, LVCMOS for USB Blaster and Power Intel MAX 10 logic
• 50 MHz oscillator, LVCMOS for PFL control Intel MAX 10 logic
• 24 MHz crystal for USB-Blaster II PHY
• 50 MHz oscillator, LVCMOS for Intel Cyclone 10 GX FPGA core
• 100 MHz oscillator, LVCMOS for Intel Cyclone 10 GX FPGA user_clk
• A programmable oscillator, LVDS for tranceivers: 644.53125 MHz by default, LVDSto FPGA tranceiver
• Programmable clock generator for FPGA logic
— 21.186 MHz LVDS for EMIF, LVDS to FPGA core
— 125 MHz LVDS for transceiver of USB3.1, LVDS to FPGA transceiver
— 125 MHz for Gigabit Ethernet, LVDS to FPGA core
— 100 MHz for FPGA logic, LVCMOS to FPGA core
• 100 MHz for PCIe system to FPGA transceiver
• User-defined reference clock input from FMC card
— 1 for FMC transceiver to FPGA transceiver
— 2 for FMC LA reference to FPGA core
— 2 for FMC clock reference to FPGA core
• One external differential input through SMA, AC coupled
• One single-ended LVCMOS clock output through SMA, DC coupled
Transceiver Interfaces
• 12 transceivers organized in two banks
• 4 channels for PCIe x4 Gen2
• 2 channels for 2 SFP+ supporting 10 GE
• 1 channel for USB3.1 SuperSpeed
• 5 channels for FMC card
Memory Interfaces
• 1 channel of x40 DDR3 @ 933 MHz
Communication Ports
• 10/100/1000Base-T Ethernet port with SGMII (LVDS)
• USB3.1 Type-C supporting SuperSpeed, backward compatible with USB2.0
• 2 SFP+ supporting 10GE
• FMC expansion card:
— 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
— 8G DisplayPort: Bitec FMC DisplayPort Daughter Card
— 6G HDMI 2.0: Bitec FMC HDMI Daughter Card
Pushbuttons
• 3 User Push Buttons
• 1 User Program selecting Pushbutton
• 1 nCONFIG Pushbutton to initiate configuration
• 1 FPGA reset Pushbutton to reset the FPGA logic
Switches
• 4 User DIP Switches
• DIP switch for MSEL
• DIP switch for JTAG chain selection
• DIP switch for clock source selection
LEDs
• 4 User LEDs
• 1 Power LED
• 1 Config Done LED
• PFL Load/Error LED
• PFL Program Number LED
• Ethernet LEDs
• SFP+ LEDs
Heatsink and Fan
Heatsink with fan
Power
• 12 V power input from ATX 2 x 4 power connector
• 12 V external power adaptor input
• 12 V power input from PCIe system
• On/Off Slide Power Switch
• On-board power measurement and management
• Adjustable FMC+ power regulator
• Power Failure Monitor
• Power-off discharge circuit
Dimensions
Full height PCIe add-in card 4.376" (Height) x 7" (Length)
Operating Environment
Ambient Temperature: 0℃ to 45℃

图3.Cyclone 10 GX FPGA开发板外形图

图4.Cyclone 10 GX FPGA开发板框图

图5.Cyclone 10 GX FPGA开发板电路图(1)

图6.Cyclone 10 GX FPGA开发板电路图(2)

图7.Cyclone 10 GX FPGA开发板电路图(3)

图8.Cyclone 10 GX FPGA开发板电路图(4)

图9.Cyclone 10 GX FPGA开发板电路图(5)

图10.Cyclone 10 GX FPGA开发板电路图(6)

图11.Cyclone 10 GX FPGA开发板电路图(7)

图12.Cyclone 10 GX FPGA开发板电路图(8)

图13.Cyclone 10 GX FPGA开发板电路图(9)

图14.Cyclone 10 GX FPGA开发板电路图(10)

图15.Cyclone 10 GX FPGA开发板电路图(11)

图16.Cyclone 10 GX FPGA开发板电路图(12)

图17.Cyclone 10 GX FPGA开发板电路图(13)

图18.Cyclone 10 GX FPGA开发板电路图(14)

图19.Cyclone 10 GX FPGA开发板电路图(15)

图20.Cyclone 10 GX FPGA开发板电路图(16)

图21.Cyclone 10 GX FPGA开发板电路图(17)

图22.Cyclone 10 GX FPGA开发板电路图(18)

图23.Cyclone 10 GX FPGA开发板电路图(19)

图24.Cyclone 10 GX FPGA开发板电路图(20)

图25.Cyclone 10 GX FPGA开发板电路图(21)

图26.Cyclone 10 GX FPGA开发板电路图(22)

图27.Cyclone 10 GX FPGA开发板电路图(23)

图28.Cyclone 10 GX FPGA开发板电路图(24)

图29.Cyclone 10 GX FPGA开发板电路图(25)

图30.Cyclone 10 GX FPGA开发板电路图(26)

图31.Cyclone 10 GX FPGA开发板电路图(27)

图32.Cyclone 10 GX FPGA开发板电路图(28)

图33.Cyclone 10 GX FPGA开发板电路图(29)

图34.Cyclone 10 GX FPGA开发板电路图(30)

图35.Cyclone 10 GX FPGA开发板电路图(31)

图36.Cyclone 10 GX FPGA开发板电路图(32)

图37.Cyclone 10 GX FPGA开发板电路图(33)

图38.Cyclone 10 GX FPGA开发板电路图(34)

图39.Cyclone 10 GX FPGA开发板电路图(35)

图40.Cyclone 10 GX FPGA开发板电路图(36)

图41.Cyclone 10 GX FPGA开发板电路图(37)

图42.Cyclone 10 GX FPGA开发板电路图(38)

图43.Cyclone 10 GX FPGA开发板电路图(39)

图44.Cyclone 10 GX FPGA开发板电路图(40)

图45.Cyclone 10 GX FPGA开发板电路图(41)

图46.Cyclone 10 GX FPGA开发板电路图(42)

图47.Cyclone 10 GX FPGA开发板电路图(43)
详情请见:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug-c10-gx-fpga-devl-kit.pdf
以及https://www.altera.com/content/dam/altera-www/global/en_US/support/boards-kits/cyclone10/c10gx-dev-kits-board-a1-release.pdf
c10gx-51001.pdf
c10gx-51002.pdf
c10gx-dev-kits-board-a1-release.pdf

 
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